The present invention relates generally to a logic circuit for zero detection, and more particularly to a logic circuit for detecting a zero result of an addition without performing the addition for two vectors containing signed integer values.
The SRT algorithm is a square root algorithm named after its originators, Sweeney, Robertson and Tocher. A hardware SRT implementation of a divide and square root algorithm uses a redundant data format to perform the inner loop of the algorithm. The partial remainder of the iteration is represented in two vectors of a length N containing signed integer numbers in the 2's complement representation. N is defined by the precision of the operands. The information whether the remainder is zero or not is needed for the rounding step of the operation.
The problem of fast detection whether two numbers sum to zero is not unique to SRT engines. It occurs in several corners of floating-point unit design; for example, in the exponent logic when checking for corner cases like overflow and underflow.
One known solution of the zero check is to use an adder. This method adds two input vectors and checks the result for any non-zero bit. The logic depth of such an implementation is 2*log(n)+3 without the or-reduction. The drawbacks of the method include additional hardware of an N-bit adder, the deeper logic tree to compute the result, and more power consumption.
Another known solution of the zero check is to use a leading zero anticipator with an additional compare of the result of the leading zero anticipator. The zero check using a leading zero anticipator uses two input vectors, performs the leading zero anticipation without adding the two vectors, and compares the result against the number of bits of the vectors. The logic depth of this implementation is between log(n)+7 and 1.5*log(n)+5. The drawbacks of the method include the additional leading zero anticipator, the deeper logic tree to compute the result, and more power consumption.